1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a data output circuit for outputting data read from memory cells.
2. Background Art
Since a semiconductor memory device is developed having high density and large capacity, it is necessary to increase the operational speed of the memory device when implemented in an integrated circuit. To this end, the integrated circuit is provided with a voltage increase circuit, a voltage pumping circuit, in order to produce a voltage rise Vpp that is greater than the source voltage when the operational voltage of the integrated circuit becomes low. Also, the integrated circuit is provided with an equalizer or pre-charge circuit to speed up the enabling of data signals. As is well-known in the art, achieving high speed data access depends significantly on the operational speed of the data output circuit (which comprises a data output buffer and a data output driver) for outputting the data read from the memory cells and for sensing data from the memory cells. The data output circuit outputs the data read from the memory cells to a system of high impedance external to the integrated circuit. Therefore, a transistor of the data output driver should have a larger channel size than transistors of the other circuits in order to increase the voltage level of the data to be ready for the large loading of a Dout Pin. In this case, the voltage level of the signal controlling the data output driver should be large enough to drive a transistor having a large channel.
A conventional data output circuit shown in FIG. 1 comprises input means 1-4 connected to data buses DB and DBB, output means 21 and 22 consisting of pull-up and pull-down transistors, pull-up control circuit 5-18 for controlling a pull-up transistor 21, and pull-down control circuit 19-20 for controlling the pull-down transistor 22. The pull-up and pull-down control circuits are controlled by a signal PITRST for enabling the output of the data output circuit. In the pull-up control circuit 5-18, a first capacitor 7 with one electrode connected to the output terminal of the first NAND gate 5 pumps up the voltage level of node n1, pre-charged at a voltage level of Vcc-Vth, to a higher level than the pre-charge voltage level when enabling the integrated circuit. A second capacitor 13 with one electrode connected via an inverter 12 to the output of the first NAND gate 5 pumps up the voltage level of node n2, pre-charged at a voltage level of Vcc-Vth, to a higher level than the pre-charge voltage level when outputting data during the enabling of the integrated circuit.
During operation of the conventional circuit shown in FIG. 1, the output data Dout of the data output circuit maintains a tri-state level provided by the system external to the integrated circuit in order to prevent the accessing of invalid data. In addition, the Dout pin or pad of the integrated circuit causes large self-loading, therefore, the sizes of pull-up and pull-down transistors 21 and 22 are made considerably larger than those of the other transistors. The pull-up control circuit 5-18 is provided with first and second pumping capacitors 7 and 13 comprising MOS transistors as shown in FIG. 1 in order to sufficiently drive the pull-up transistor having large channel size. Node n1 is respectively pre-charged between voltage levels Vcc-Vth and Vcc+2 Vth by means of the NMOS transistor when the integrated circuit is powered up and enabled. Node n2 is pre-charged to the Vcc-Vth level by means of NMOS transistor 16 when the integrated circuit is powered up. Node n2 is pre-charged to a full Vcc level by means of the fully turned-on NMOS transistor 15 when the integrated circuit is enabled. Two NMOS transistors 10 and 11 having channels connected in series form a clamper device designed to keep the voltage of node n1 to the Vcc+2 Vth level.
Hence, when data signal DBB is in a logical low level and the signal PITRST is in a logical high level, the output signal of the first NAND gate 5 becomes logical low. The coupling of capacitor 7 causes the voltage level of node n1 to drop down from the Vcc+2 Vth level turning off the channel of NMOS transistor 15. The logical high level output signal of inverter 12 causes the coupling effect of the second capacitor 13 to raise the voltage level of node n2 up to 2 Vcc. The logical low signal of the first NAND gate 5 turns on PMOS transistor 17 and then the pull-up transistor 21 in order to output the high level data from the integrated circuit. However, when data signal DB is logical low level, the pull-up transistor 21 is turned off and the pull-down transistor 22 turned on so as to output the low level data from the integrated circuit.
The circuit shown in FIG. 1 has several disadvantages. Capacitors consisting of MOS transistors are used to pump up voltage levels, therefore, an abrupt rise in voltage can destroy the junctions of the capacitors. The layout area occupied by a MOS capacitor is considerably larger than other devices, thus making it difficult to achieve high density. The pumped up voltage requires a circuit such as keeper to maintain a constant voltage level. Further, when the output Dout of the circuit shown in FIG. 1 is in the tri-state, the gate voltages of pull-up and pull-down transistors 21 and 22 should be in logical low level in order to turn off the transistors, and nodes n1 and n2 should be pre-charged with the voltage level Vcc-Vth. Consequently, a transistor (i.e., PMOS transistor 17) is required for properly-switching pull-up and pull-down transistors 21 and 22, thereby impairing the operational speed.